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LTC1143 Dual High Efficiency Step-Down Switching Regulator Controller
FEATURES
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DESCRIPTION
The LTC1143 is a dual step-down switching regulator controller featuring automatic Burst ModeTM operation to maintain high efficiencies at low output currents. This device is composed of two separate regulator blocks, each driving an external power MOSFET at switching frequencies exceeding 400kHz using a constant off-time current mode architecture providing constant ripple current in the inductor. The operating current level for both regulators is userprogrammable via an external current sense resistor. Wide input supply range allows operation from 4V to 14V (16V maximum). Constant off-time architecture provides low dropout regulation limited only by the RDS(ON) of the external MOSFET and resistance of the inductor and current sense resistor. The LTC1143 is ideal for applications requiring dual output voltages with high conversion efficiencies over a wide load current range in a small amount of board space.
Burst Mode is a trademark of Linear Technology Corporation.
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Dual Outputs: 3.3V and 5.0V Very High Efficiency: Over 95% Possible Current Mode Operation for Excellent Line and Load Transient Response High Efficiency Maintained Over 3 Decades of Output Current Low Standby Current at Light Loads: 160A/Output Independent Micropower Shutdown: IQ < 40A Wide VIN Range: 4V to 16V Very Low Dropout Operation: 100% Duty Cycle Available in Narrow 16-Pin SOIC Package
APPLICATIONS
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Notebook and Palmtop Computers Battery-Operated Digital Devices Portable Instruments DC Power Distribution Systems
TYPICAL APPLICATION
+
CIN3 22F 25V x2 0.22F P-CH Si9430DY 4 1 1000pF 16 SENSE - 3 13 VIN3 P-DRIVE 3 SENSE + 3
VIN 5.2V TO 14V
0V = NORMAL >1.5V = SHUTDOWN 2 10 SHUTDOWN 3 SHUTDOWN 5
5 VIN5 P-DRIVE 5 SENSE + 5 12 9
VOUT3 3.3V/2A
RSENSE3 0.05
L1 50H
LTC1143 SENSE - 5 8
+
COUT3 220F 10V x2
D1 MRD330 GND3 3 CT3 14 CT3 560pF ITH3 15 RC3 1k 3300pF CC3 ITH5 7 RC5 1k 3300pF CC5 CT5 6 CT5 390pF GND5 11
RSENSE3, RSENSE5: KRL SL-1/2-CI-0R050J
L1: COILTRONICS CTX50-2-MP L2: COILTRONICS CTX50-2-MP
NOTE: COMPONENTS OPTIMIZED FOR HIGHEST EFFICIENCY, NOT MINIMUM BOARD SPACE.
Figure 1. High Efficiency Dual 3.3V/5V
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0.22F P-CH Si9430DY L2 50H
CIN5 22F 25V x2
RSENSE5 0.05
VOUT5 5V/2A
1000pF
D2 MBRD330
+
COUT5 220F 10V x2
1143 F01
1
LTC1143
ABSOLUTE MAXIMUM RATINGS
Input Supply Voltage (Pins 5,13) ............... 16V to -0.3V Continuous Output Current (Pins 4,12) ................ 50mA Sense Voltages (Pins 1, 8, 9, 16).............. 13V to -0.3V Operating Ambient Temperature Range ....... 0C to 70C Extended Commercial Temperature Range............................. -40C to 85C Junction Temperature (Note 1) ............................. 125C Storage Temperature Range .................. -65C to 150C Lead Temperature (Soldering, 10 sec).................. 300C
PACKAGE/ORDER INFORMATION
TOP VIEW SENSE 3 1 SHUTDOWN 3 2 GND3 3 P-DRIVE 3 4 VIN5 5 CT5 6 ITH5 7 SENSE-5 8
+
16 SENSE-3 15 ITH3 14 CT3 13 VIN3 12 P-DRIVE 5 11 GND5 10 SHUTDOWN 5 9 SENSE+5
ORDER PART NUMBER LTC1143CS
S PACKAGE 16-LEAD PLASTIC SOIC
TJMAX = 125C, JA = 95C/W
Consult factory for Industrial and Military grade parts.
ELECTRICAL CHARACTERISTICS
SYMBOL VOUT PARAMETER Regulated Output Voltage 3.3V Output 5V Output Output Voltage Line Regulation Output Voltage Load Regulation 3.3V Output 5V Output Output Ripple (Burst Mode) Input DC Supply Current (Note 2) Normal Mode Sleep Mode Shutdown Current-Sense Threshold Voltage 3.3V Section 5V Section Shutdown Pin Threshold Shutdown Pin Input Current CT Pin Discharge Current Off-Time (Note 3) Driver Output Transition Times CONDITIONS
TA = 25C, VIN3 = VIN5 = 10V, V2 = V10 = 0V, unless otherwise noted.
MIN
q q
TYP 3.33 5.05 0 40 60 50 1.6 160 10 25 150 25 150 0.8 1.2 70 2 5 100
MAX 3.43 5.20 40 65 100
UNITS V V mV mV mV mVP-P
VIN3, VIN5 = 9V ILOAD = 700mA ILOAD = 700mA VIN3, VIN5 = 7V to 12V, ILOAD = 50mA Figure 1 Circuit 5mA < ILOAD < 2.0A 5mA < ILOAD < 2.0A ILOAD = 0A 4V < VIN3, VIN5 < 12V 4V < VIN3 < 12V, 6V < VIN5 < 12V V2 = V10 = 2.1V, 4V < VIN3, VIN5 < 12V V16 = VOUT + 100mV (Forced) V16 = VOUT - 100mV (Forced) V8 = VOUT + 100mV (Forced) V8 = VOUT - 100mV (Forced) 0V < VSHUTDOWN = < 8V, VIN3, VIN5 = 16V VOUT in Regulation, VSENSE- = VOUT VOUT = 0V CT = 390pF, ILOAD = 700mA CL = 3000pF (Pins 4, 12), VIN = 6V
3.23 4.90 -40
VOUT VOUT
q q
VOUT I5, I13
2.1 230 20
V1 to V16 V8 to V9 V2, V10 I2, I10 I6, I14 tOFF tr, tf
q q
130 130 0.6 50
170 170 2 5 90 10 6 200
q
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mA A A mV mV mV mV V A A A s ns
LTC1143 ELECTRICAL CHARACTERISTICS
SYMBOL VOUT PARAMETER Regulated Output Voltage 3.3V Output 5V Output Input DC Supply Current (Note 2) Normal Mode Sleep Mode Shutdown Current Sense Threshold Voltage 3.3V Section 5V Section Shutdown Pin Threshold Off-Time (Note 3) CT = 390pF, ILOAD = 700mA CONDITIONS VIN3, VIN5 = 9V ILOAD = 700mA ILOAD = 700mA 4V < VIN3, VIN5 < 12V 4V < VIN3, VIN5 < 12V V2 = V10 = 2.1V, 4V < VIN3, VIN5 < 12V V16 = VOUT + 100mV (Forced) V16 = VOUT - 100mV (Forced) V8 = VOUT + 100mV (Forced) V8 = VOUT - 100mV (Forced)
-40C TA 85C (Note 4), VIN3 = VIN5 = 10V, unless otherwise noted.
MIN 3.17 4.85 TYP 3.33 5.05 1.6 160 10 25 150 25 150 0.8 5 MAX 3.4 5.2 2.4 260 22 UNITS V V mA A A mV mV mV mV V s
I5, I13
V1 to V16 V8 to V9 V2, V10 tOFF
125 125 0.55 3.8
175 175 2 6
The q denotes specifications which apply over the operating temperature range. Note 1: TJ is calculated from the ambient temperature TA and power dissipation PD according to the following formula: LTC1143CS: TJ = TA + (PD x 120C/W) Note 2: This supply current is for one regulator block. Total supply current is the sum of pin 5 and pin 13 currents. Dynamic supply current
is higher due to the gate charge being delivered at the switching frequency. See Applications Information. Note 3: In applications where RSENSE is placed at ground potential, the off-time increases approximately 40%. Note 4: The LTC1143 is not tested and quality assurance sampled at -40C to 85C. These specifications are guaranteed by design and/or correlation.
TYPICAL PERFORMANCE CHARACTERISTICS
5V Output Efficiency
100 VIN = 6V 95
EFFICIENCY (%)
VIN = 10V 85 80 75 70 1 10 100 1000
LTC1143 G01
EFFICIENCY (%)
90
EFFICIENCY (%)
LOAD CURRENT (mA)
UW
3.3V Output Efficiency
100 95 VIN = 5V 90 85 80 75 70 1 10 100 1000
LTC1143 G02
5V Efficiency vs Input Voltage
100 98 96 94 92 90 88 86 84 82 80 0 4 12 8 INPUT VOLTAGE (V) 16
LTC1143 G03
FIGURE 1 CIRCUIT
ILOAD = 1A
VIN = 10V
ILOAD = 100mA
LOAD CURRENT (mA)
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LTC1143 TYPICAL PERFORMANCE CHARACTERISTICS
3.3V Efficiency vs Input Voltage
100 98 96
EFFICIENCY (%)
FIGURE 1 CIRCUIT VOUT = 3.3V
94 92 90 88 86 84 82 80 0 4 12 8 INPUT VOLTAGE (V) 16
LTC1143 G04
VOUT (mV)
VOUT (mV)
ILOAD = 1A ILOAD = 100mA
DC Supply Current
2.1 1.8 NOT INCLUDING GATE CHARGE CURRENT ACTIVE MODE PINS 5, 13
NORMALIZED FREQUENCY
SUPPLY CURRENT (mA)
1.5 1.2 0.9 0.6 0.3 0 0 2 4
SUPPLY CURRENT (A)
PER REGULATOR BLOCK
SLEEP MODE 6 8 10 12 14 INPUT VOLTAGE (V) 16 18
Gate Charge Supply Current
14 12
GATE CHARGE CURRENT (mA)
10 8 6 4
QP = 100nC
SENSE VOLTAGE (mV)
OFF-TIME (s)
QP = 29nC 2 0 20 80 200 260 140 OPERATING FREQUENCY (kHz)
LTC1143 G10
4
UW
LTC1143 * G07
Line Regulation
40 30 20 10 0 -10 -20 -30 -40 0 4 12 8 INPUT VOLTAGE (V) 16
LTC1143 G05
Load Regulation
20 FIGURE 1 CIRCUIT RSENSE = 0.05 VIN = 6V VIN = 12V
FIGURE 1 CIRCUIT ILOAD = 1A
0 -20 -40 -60 -80 -100 0 0.5 VIN = 6V
VIN = 12V VOUT = 5V VOUT = 3.3V 1.5 2.0 1.0 LOAD CURRENT (A) 2.5
LTC1143 G06
Supply Current in Shutdown
20 18 16 14 12 10 8 6 4 2 0 0 2 4 6 8 10 12 14 INPUT VOLTAGE (V) 16 18
0.2 0 1.6
Operating Frequency vs VIN - VOUT
VOUT = 5V 1.4 0C 1.2 25C 1.0 0.8 0.6 0.4 70C
PER REGULATOR BLOCK PINS 5, 13 VSHUTDOWN = 2V
0
2
4
6
8
10
12
(VIN - VOUT) VOLTAGE (V)
LTC1143 G08
LTC1143 G09
Off-Time vs VOUT
80 70 60 50 40 30 20 10 0 0 VOUT = 3.3V 1 3 4 2 OUTPUT VOLTAGE (V) 5
LTC1143 G11
Current Sense Threshold Voltage
175
VSENSE = VOUT
150 125 100 75 50 25 0 0 20
MAXIMUM THRESHOLD
VOUT = 5V
MINIMUM THRESHOLD
60 40 TEMPERATURE (C)
80
100
LTC1143 G12
LTC1143
PIN FUNCTIONS
SENSE+3 (Pin 1): The (+) Input to the 3.3V Section Current Comparator. A built in offset between pins 1 and 16 in conjunction with RSENSE 3 sets the current trip threshold for the 3.3V section. SHUTDOWN 3 (Pin 2): When grounded, the 3.3V section operates normally. Pulling pin 2 high holds the MOSFET off and puts the 3.3V section in micropower shutdown mode. Requires CMOS logic level signal with tr, tf < 1s. Do not "float" pin 2. GND3 (Pin 3): 3.3V Section Ground. Two independent ground lines must be routed separately from other grounds to: 1) the (-) terminal of the 3.3V section output capacitor, and 2) the cathode of the Schottky diode D1 and (-) terminal of CIN3 (See Figures 1 and 9). P-DRIVE 3 (Pin 4): High Current Drive for Top P-Channel MOSFET, 3.3V Section. Voltage swing at this pin is from VIN3 to ground. VIN5 (Pin 5): Supply Pin, 5V Section. Must be closely decoupled to 5V power ground pin 11. CT5 (Pin 6): External capacitor CT5 from pin 6 to ground sets the operating frequency for the 5V section. (The actual frequency is also dependent upon the input voltage.) ITH5 (Pin 7): Gain Amplifier Decoupling Point, 5V Section. The 5V section current comparator threshold increases with the pin 7 voltage. SENSE- 5 (Pin 8): Connects to internal resistive divider which sets the output voltage for the 5V section. Pin 8 is also the (-) input for the current comparator on the 5V section. SENSE+ 5 (Pin 9): The (+) Input to the 5V Section Current Comparator. A built-in offset between pins 9 and 8 in conjunction with RSENSE 5 sets the current trip threshold for the 5V section. SHUTDOWN 5 (Pin 10): When grounded, the 5V section operates normally. Pulling pin 10 high holds the 5V section MOSFET off and puts the 5V section in micropower shutdown mode. Requires CMOS logic level signal with tr, tf < 1s. Do not "float" pin 10. GND5 (Pin 11): 5V Section Ground. Two independent ground lines must be routed separately from other grounds to: 1) the (-) terminal of the 5V section output capacitor, and 2) the cathode of the Schottky diode D2 and (-) terminal of CIN5 (See Figures 1 and 9). P-DRIVE 5 (Pin 12): High Current Drive for Top P-Channel MOSFET, 5V Section. Voltage swing at this pin is from VIN5 to ground. VIN3 (Pin 13): Supply Pin, 3.3V Section. Must be closely decoupled to 3.3V power ground pin 3. CT3 (Pin 14): External capacitor CT3 from pin 14 to ground sets the operating frequency for the 3.3V section. (The actual frequency is also dependent upon the input voltage.) ITH3 (Pin 15): Gain Amplifier Decoupling Point, 3.3V Section. The 3.3V section current comparator threshold increases with the pin 15 voltage. SENSE - 3 (Pin 16): Connects to internal resistive divider which sets the output voltage for the 3.3V section. Pin 16 is also the (-) input for the current comparator on the 3.3V section.
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LTC1143
FUNCTIONAL DIAGRA
SLEEP
+
S
Q S VTH1
-
VTH2
- +
T
14(6) CT
OFF-TIME CONTROL
OPERATION
Refer to Functional Diagram and Figure 1.
The LTC1143 consists of two individual regulator blocks each using current mode, constant off-time architectures to switch an external power MOSFET. The two regulators are internally set to provide output voltages of 3.3V and 5V. Operating frequency is individually set on each section by external capacitors at the timing capacitor pins 6 and 14. The output voltage is sensed by an internal voltage divider connected to Sense - pin 16 (8). A voltage comparator V and a gain block G compare the divided output voltage with a reference voltage of 1.25V. To optimize efficiency, the LTC1143 automatically switches between two modes of operation, burst and continuous. The voltage comparator is the primary control element when the device is in Burst Mode operation, while the gain block controls the output voltage in continuous mode. During the switch "ON" cycle in continuous mode, current comparator C monitors the voltage between pins 1 (9) and 16 (8) connected across an external shunt in series with the inductor. When the voltage across the shunt reaches its threshold value, the P-drive output is switched to VIN, turning off the P-channel MOSFET. The timing capacitor connected to pin 14 (6) is now allowed to discharge at a rate determined by the off-time controller. The discharge
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Only one regulator block shown. Pin numbers are for 3.3V (5V) sections.
13(5) VIN SENSE + 1(9) 3(11) GROUND SENSE - 16(8)
4(12)
P-DRIVE
-
V
+
-
C 25mV TO 150mV
+
ITH 15(7)
-
+
VOS 13k G
5pF
- +
1.25V 100k
VIN SENSE -
SHUTDOWN 2(10) REFERENCE
1143 FD
current is made proportional to the output voltage [measured by pin 16 (8)] to model the inductor current, which decays at a rate which is also proportional to the output voltage. When the voltage on the timing capacitor has discharged past VTH1, comparator T trips, setting the flip-flop. This causes the P-drive output to go low turning the P-channel MOSFET back on. The cycle then repeats. As the load current increases, the output voltage decreases slightly. This causes the output of the gain stage [pin 15 (7)] to increase the current comparator threshold, thus tracking the load current. The sequence of events for Burst Mode operation is very similar to continuous operation with the cycle interrupted by the voltage comparator. When the output voltage is at or above the desired regulated value, the P-channel MOSFET is held off by comparator V and the timing capacitor continues to discharge below VTH1. When the timing capacitor discharges past VTH2, voltage comparator S trips, causing the internal sleep line to go low. The circuit now enters sleep mode with the power MOSFET turned off. In sleep mode a majority of the circuitry is
LTC1143
OPERATION
turned off, dropping the quiescent current from 1.6mA to 160A (for one regulator block). The load current is now being supplied from the output capacitor. When the output voltage has dropped by the amount of hysteresis in comparator V, the P-channel MOSFET is again turned on and the process repeats. To avoid the operation of the current loop interfering with Burst Mode operation, a built-in offset (VOS) is incorporated in the gain stage. This prevents the current compara-
APPLICATIONS INFORMATION
The basic LTC1143 application circuit is shown in Figure 1. External component selection is driven by the load requirement and begins with the selection of RSENSE. Once RSENSE is known, CT and L can be chosen. Next, the power MOSFET and D1 are selected. Finally, CIN and COUT are selected and the loop is compensated. Since the 3.3V and 5V sections are identical, the process of component selection is the same for both sections. The circuit shown in Figure 1 can be configured for operation up to an input voltage of 16V. RSENSE Selection for Output Current RSENSE is chosen based on the required output current. The LTC1143 current comparators have a threshold range which extends from a minimum of 25mV/RSENSE to a maximum of 150mV/RSENSE. The current comparator threshold sets the peak of the inductor ripple current, yielding a maximum output current IMAX equal to the peak value less half the peak-to-peak ripple current. For proper Burst Mode operation, IRIPPLE(P-P) must be less than or equal to the minimum current comparator threshold. Since efficiency generally increases with ripple current, the maximum allowable ripple current is assumed, i.e., IRIPPLE(P-P) = 25mV/RSENSE. (See CT and L Selection for Operating Frequency). Solving for RSENSE and allowing a margin for variations in the LTC1143 and external component values yields:
0 0 1 3 4 2 MAXIMUM OUTPUT CURRENT (A) 5
1143 F02
RSENSE ()
RSENSE = 100mV IMAX
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Refer to Functional Diagram and Figure 1
tor threshold from increasing until the output voltage has dropped below a minimum threshold. Using constant off-time architecture the operating frequency is a function of the input voltage. To minimize the frequency variation as dropout is approached, the off-time controller increases the discharge current as VIN drops below VOUT + 1.5V. In dropout the P-channel MOSFET is turned on continuously (100% duty cycle), providing extremely low dropout operation.
A graph for selecting RSENSE versus maximum output current is given in Figure 2.
0.20
0.15
0.10
0.05
Figure 2. Selecting RSENSE
The load current below which Burst Mode operation commences, IBURST, and the peak short circuit current, ISC(PK), both track IMAX. Once RSENSE has been chosen, IBURST and ISC(PK) can be predicted from the following:
IBURST 15mV RSENSE
ISC(PK) = 150mV RSENSE
The LTC1143 automatically extends tOFF during a short circuit to allow sufficient time for the inductor current to decay between switch cycles. The resulting ripple current causes the average short-circuit current ISC(AVG) to be reduced to approximately IMAX.
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LTC1143
APPLICATIONS INFORMATION
L and CT Selection for Operating Frequency Each regulator section of LTC1143 uses a constant offtime architecture with tOFF determined by an external timing capacitor CT. Each time the P-channel MOSFET switch turns on the voltage on CT is reset to approximately 3.3V. During the off-time, CT is discharged by a current which is proportional to VOUT. The voltage on CT is analogous to the current in inductor L, which likewise decays at a rate proportional to VOUT. Thus the inductor value must track the timing capacitor value. The value of CT is calculated from the desired continuous mode operating frequency:
VIN - VOUT 1 CT = 4xf V +V 1.3 x 10 IN D
)
)
Where VD is the drop across the diode. A graph for selecting CT versus frequency including the effects of input voltage is given in Figure 3.
1000 VSENSE = VOUT = 5V 800
CAPACITANCE (pF)
600 VIN = 12V
400 VIN = 7V
200
VIN = 10V
0 0 50 150 200 100 FREQUENCY (kHz) 250
300
LTC1143 F03
Figure 3. Timing Capacitor Value
As the operating frequency is increased the gate charge losses will be higher, reducing efficiency (see Efficiency Considerations). The complete expression for operating frequency of the circuit in Figure 1 is given by:
f= 1 tOFF
)
1-
VOUT VIN
)
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Where:
tOFF = 1.3 x 104 x CT x
))
VREG VOUT
VREG is the desired output voltage (i.e., 5V, 3.3V). VOUT is the measured output voltage. Thus VREG/V OUT = 1 in regulation. Note that as VIN decreases, the frequency decreases. When the input to output voltage differential drops below 1.5V for a particular section, the LTC1143 reduces tOFF in that section by increasing the discharge current in CT. This prevents audible operation prior to dropout. Once the frequency has been set by CT, the inductor L must be chosen to provide no more than 25mV/RSENSE of peakto-peak inductor ripple current. This results in a minimum required inductor value of: LMIN = 5.1 x 105 x RSENSE x CT x VREG As the inductor value is increased from the minimum value, the ESR requirements for the output capacitor are eased at the expense of efficiency. If too small an inductor is used the inductor current will become discontinuous before the LTC1143 enters Burst Mode operation. A consequence of this is that the LTC1143 will delay entering Burst Mode operation and efficiency will be degraded at low currents. Inductor Core Selection Once the minimum value for L is known, the type of inductor must be selected. The highest efficiency will be obtained using Ferrite, Kool M(R) or Molypermalloy (MPP) cores. Lower cost powdered iron cores provide suitable performance, but cut efficiency by 3% to 7%. Actual core loss is independent of core size for a fixed inductor value, but it is very dependent on inductance selected. As inductance increases, core losses go down. Unfortunately, increased inductance requires more turns of wire and therefore copper losses will increase. Ferrite designs have very low core loss, so design goals can concentrate on copper loss and preventing saturation.
Kool M is a registered trademark of Magnetics, Inc.
LTC1143
APPLICATIONS INFORMATION
Ferrite core material saturates "hard," which means that inductance collapses abruptly when the peak design current is exceeded. This results in an abrupt increase in inductor ripple current and consequent output voltage ripple which can cause Burst Mode operation to be falsely triggered. Do not allow the core to saturate! Kool M (from Magnetics, Inc.) is a very good, low loss core material for toroids with a "soft" saturation characteristic. Molypermalloy is slightly more efficient at high ( > 200 kHz) switching frequencies but quite a bit more expensive. Toroids are very space efficient, especially when you can use several layers of wire. Because they generally lack a bobbin, mounting is more difficult. However, new designs for surface mount are available from Coiltronics and Beckman Industrial Corporation which do not increase the height significantly. Power MOSFET Selection An external power MOSFET must be selected for use with each section of the LTC1143. The main selection criteria for the power MOSFETs are the threshold voltage VGS(TH) and on resistance RDS(ON). The minimum input voltage determines whether a standard threshold or logic-level threshold MOSFET must be used. For VIN > 8V, standard threshold MOSFETs (VGS(TH) < 4V) may be used. If VIN is expected to drop below 8V, logic-level threshold MOSFETs (VGS(TH) < 2.5V) are strongly recommended. When logic-level MOSFETs are used, the LTC1143 supply voltage must be less than the absolute maximum VGS ratings for the MOSFET. The maximum output current IMAX determines the RDS(ON) requirement for the two MOSFETs. When the LTC1143 is operating in continuous mode, the simplifying assumption can be made that either the MOSFET or Schottky diode is always conducting the average load current. The duty cycles for the MOSFET and diode are given by: From the duty cycles the required RDS(ON) for each MOSFET can be derived:
V P-Ch Duty Cycle = OUT VIN (V - VOUT + VD) Schottky Diode Duty Cycle = IN VIN
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P-Ch RDS(ON) =
VIN x PP VOUT x IMAX2 x (1 + P)
where PP is the allowable power dissipation and P is the temperature dependencies of RDS(ON). PP will be determined by efficiency and/or thermal requirements (see Efficiency Considerations). (1+ d) is generally given for a MOSFET in the form of a normalized RDS(ON) vs. temperature curve, but = 0.007/C can be used as an approximation for low voltage MOSFETs. Output Diode Selection (D1, D2) The Schottky diodes D1 and D2 shown in Figure 1 conduct during the off-time. It is important to adequately specify the diode peak current and average power dissipation so as not to exceed the diode ratings. The most stressful condition for the output diode is under short circuit (VOUT=0). Under this condition the diode must safely handle ISC(PK) at close to 100% duty cycle. Under normal load conditions the average current conducted by the diode is:
(V - VOUT + VD) IDIODE = IN (ILOAD) VIN
Remember to keep lead lengths short and observe proper grounding (see Board Layout Checklist) to avoid ringing and increased dissipation. The forward voltage drop allowable in the diode is calculated from the maximum short circuit current as:
VF PD ISC(PK)
where PD is the allowable power dissipation and will be determined by efficiency and/or thermal requirements (see Efficiency Considerations).
9
LTC1143
APPLICATIONS INFORMATION
CIN and COUT Selection In continuous mode, the source current of the P-channel MOSFET is a square wave of duty cycle VOUT/VIN. To prevent large voltage transients, a low ESR input capacitor sized for the maximum RMS current must be used. The maximum RMS capacitor current is given by:
CIN Required IRMS IMAX [VOUT(VIN - VOUT)]1/2 VIN
COUT (F)
This formula has a maximum at VIN = 2VOUT, where IRMS = IOUT/2. This simple worst case condition is commonly used for design because even significant deviations do not offer much relief. Note that capacitor manufacturer's ripple current ratings are often based on only 2000 hours of life. This makes it advisable to further derate the capacitor, or to choose a capacitor rated at a higher temperature than required. Several capacitors may also be paralleled to meet size or height requirements in the design. Always consult the manufacturer if there is any question. An additional 0.1F to 1F ceramic capacitor is also required on each VIN line (pin 5, pin 13) for high frequency decoupling. The selection of COUT is driven by the required effective series resistance (ESR). The ESR of COUT must be less than twice the value of RSENSE for proper operation of the LTC1143: COUT required ESR < 2RSENSE Optimum efficiency is obtained by making the ESR equal to RSENSE. As the ESR is increased up to 2RSENSE the efficiency degrades by less than 1%. If the ESR is greater than 2RSENSE, the voltage ripple on the output capacitor will prematurely trigger Burst Mode operation, resulting in disruption of continuous mode and an efficiency hit which can be several percent. Manufacturers such as Nichicon and United Chemicon, should be considered for high performance capacitors. The OS-CON semiconductor dielectric capacitor available
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from Sanyo has the lowest ESR size/ratio of any aluminum electrolytic at a somewhat higher price. Once the ESR requirement for COUT has been met the RMS current rating generally far exceeds the IRIPPLE(P-P) requirement. In surface mount applications multiple capacitors may have to be parallel to meet the capacitance, ESR, or RMS current handling requirements of the application. Aluminum electrolytic and dry tantalum capacitors are both available in surface mount configurations. In the case of tantalum it is critical that the capacitors are surge tested for use in switching power supplies. An excellent choice is the AVX TPS series of surface mount tantalums, available in case heights ranging from 2mm to 4mm. For example, if 200F/10V is called for in an application requiring 3mm height, (2) AVX 100F/10V (P/N TPSD 107K010) could be used. Consult the manufacturer for other specific recommendations.
1000 L = 50H RSENSE = 0.02 L = 25H RSENSE = 0.02
800
600
400 L = 50H RSENSE = 0.05
200
0 0 1 3 4 2 VIN - VOUT VOLTAGE (V) 5
1143 F04
Figure 4. Minimum Value of COUT
At low supply voltages a minimum capacitance at COUT is needed to prevent an abnormal low frequency operating mode (see Figure 4). When COUT is made too small the output ripple at low frequencies will be large enough to trip the voltage comparator. This causes Burst Mode operation to be activated when the LTC1143 would normally be in continuous operation. The output remains in regulation at all times.
LTC1143
APPLICATIONS INFORMATION
Checking Transient Response The regulator loop response can be checked by looking at the load transient response. Switching regulators take several cycles to respond to a step in DC (resistive) load current. When a load step occurs, VOUT shifts by an amount equal to ILOAD x ESR, where ESR is the effective series resistance of COUT. ILOAD also begins to charge or discharge COUT until the regulator loop adapts to the current change and returns VOUT to its steady-state value. During this recovery time VOUT can be monitored for overshoot or ringing which would indicate a stability problem. The pin 15(7) external components shown in the Figure 1 circuit will prove adequate compensation for most applications. A second, more severe transient is caused by switching in loads with large (>1F) supply bypass capacitors. The discharged bypass capacitors are effectively put in parallel with COUT causing a rapid drop in VOUT. No regulator can deliver enough current to prevent this problem if the load switch resistance is low and it is driven quickly. The only solution is to limit the rise time of the switch drive so that the load rise time is limited to approximately 25 x CLOAD. Thus a 10F capacitor would require a 250s rise time, limiting the charging current to about 200mA. Efficiency Considerations The percent efficiency of a switching regulator is equal to the output power divided by the input power times 100%. It is often useful to analyze individual losses to determine what is limiting the efficiency and which change would produce the most improvement. Percent efficiency can be expressed as: %Efficiency = 100% - (L1 + L2 + L3 + ...) where L1, L2, etc. are the individual losses as a percentage of input power. (For high efficiency circuits only small errors are incurred by expressing losses as a percentage of output power.) Although all dissipative elements in the circuit produce losses, four main sources usually account for most of the losses in LTC1143 circuits: 1) LTC1143 DC bias current 2) MOSFET gate charge current 3) I 2 R losses 4) Voltage drop of the Schottky diode. 1) The DC supply current is the current which flows into VIN (pin 13 for the 3.3V section, pin 5 for the 5V section) less the gate charge current. For VIN = 10V the LTC1143 DC supply current for each section is 160A for no load, and increases proportionally with load up to a constant 1.6mA after the LTC1143 has entered continuous mode. Because the DC bias current is drawn from VIN, the resulting loss increases with input voltage. For VIN=10V the DC bias losses are generally less than 1% for load currents over 30mA. However at very low load currents the DC bias current accounts for nearly all of the loss. 2) MOSFET gate charge current results from switching the gate capacitance of the power MOSFET. Each time a MOSFET gate is switched from low to high to low again, a packet of charge dQ moves from VIN to ground. The resulting dQ/dt is a current out of VIN which is typically much larger than the DC supply current. In continuous mode, IGATECHG = (QP). The typical gate charge for a 125m P-channel power MOSFET is 40nC. This results in IGATECHG = 4mA in 100kHz continuous operation, for a 2% to 3% typical mid-current loss with VIN = 10V. Note that the gate charge loss increases directly with both input voltage and operating frequency. This is the principal reason why the highest efficiency circuits operate at moderate frequencies. Furthermore, it argues against using a larger MOSFET than necessary to control I2R losses, since overkill can cost efficiency as well as money! 3) I2R losses are easily predicted from the DC resistances of the MOSFET, inductor, and current shunt. In continu ous mode the average output current flows through L and RSENSE, but is "chopped" between the P-channel MOSFET and Schottky diode. The MOSFET RDS(ON) multiplied by the P-channel duty cycle can be summed with the resistances of L and RSENSE to obtain I2R losses. For example, if the RDS(ON) = 0.1, RL = 0.15, and RSENSE = 0.05, then the total resistance is 0.3. This results in losses ranging from 3% to 10% as the output
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LTC1143
APPLICATIONS INFORMATION
current increases from 0.5A to 2A. I2R losses cause the efficiency to roll off at high output currents. 4) The Schottky diode is a major source of power loss at high currents and gets worse at high input voltages. The diode loss is calculated by multiplying the forward voltage drop times the Schottky diode duty cycle multiplied by the load current. For example, assuming a duty cycle of 50% with a Schottky diode forward voltage drop of 0.4V, the loss increases from 0.5% to 8% as the load current increases from 0.5A to 2A. If Schotky diode losses routinely exceed 5% consider using the synchronously switched LTC1142. Figure 5 shows how the efficiency losses in one section of a typical LTC1143 regulator end up being apportioned. The gate charge loss is responsible for the majority of the efficiency lost in the mid-current region. If Burst Mode operation was not employed at low currents, the gate charge loss alone would cause efficiency to drop to unacceptable levels. With Burst Mode operation, the DC supply current represents the lone (and unavoidable) loss component which continues to become a higher percentage as output current is reduced. As expected, the I2R losses and Schottky diode loss dominate at high load currents.
100 GATE CHARGE 95
12 LTC1143 I
I2R
EFFICIENCY (%)
Q
90
SCHOTTKY DIODE
85
80 0.01
0.03
0.3 1 0.1 OUTPUT CURRENT (A)
3
LTC1143 * F05
Figure 5. Efficiency Loss
Other losses including CIN and COUT ESR dissipative losses, MOSFET switching losses, and inductor core losses, generally account for less than 2% total additional loss.
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Design Example As a design example, assume VIN = 12V(nominal), 5V section, IMAX = 2A, and = 200kHz, RSENSE, CT, and L can immediately be calculated: RSENSE5 = 100mV / 2 = 0.05 tOFF = (1/200kHz) x [1 - (5/12)] = 2.92s CT5 = 2.92s/(1.3 x 104) = 220pF L2MIN = 5.1 x 105 x 0.05 x 220pF x 5V = 28H Assume that the MOSFET dissipation is to be limited to PP = 250mW. If TA = 50C and the thermal resistance of the MOSFET is 50C/W, then the junction temperatures will be 63C and P = N = 0.007(63-25) = 0.27. The required RDS(ON) for the MOSFET can now be calculated:
P-Ch RDS(ON) = 12(0.25) = 0.12 5(2)2 (1.27)
The P-channel requirement can be met by a Si9430DY. Note that the most stringent requirement for the Schottky diode is with VOUT = 0 (i.e. short circuit). During a continuous short circuit, the worst case Schottky diode dissipation rises to:
PD = ISC(AVG) x VD x 1-
)
VOUT VIN
)
With the 0.05 sense resistor ISC(AVG) = 2A will result, increasing the 0.4V Schottky diode dissipation to 0.8W. CIN will require an RMS current rating of at least 1A at temperature, and COUT will require an ESR of 0.05 for optimum efficiency. Now allow VIN to drop to its minimum value. At lower input voltages the operating frequency will decrease and the P-channel will be conducting most of the time causing its power dissipation to increase. At VIN(MIN) = 7V, the frequency shifts to 49kHz and the P-channel power dissipation increases to 435mW. Check to assure the maximum temperature of the P-channel is not exceeded.
LTC1143
APPLICATIONS INFORMATION
Troubleshooting Hints Since efficiency is critical to LTC1143 applications it is very important to verify that the circuit is functioning correctly in both continuous and Burst Mode operation. The waveform to monitor is the voltage on the timing capacitor pin 14 and pin 6. In continuous mode (ILOAD > IBURST) the voltage on the CT pin should be a sawtooth with a 0.9VP-P swing. This voltage should never dip below 2V as shown in Figure 7a. When load currents are low (ILOAD < IBURST) Burst Mode operation occurs. The voltage on the CT pin now falls to ground for periods of time as shown in Figure 7b. If pin 14 or pin 6 is observed falling to ground at high output currents, it indicates poor decoupling or improper grounding. Refer to the Board Layout Checklist.
3.3V
(a) CONTINUOUS MODE OPERATION 3.3V
(b) Burst Mode OPERATION
Figure 7. CT Waveforms
Auxiliary Windings--Suppressing Burst Mode Operation The LTC1143 being a nonsynchronous switch has the normal limitation that the power drawn from the inductor primary winding must not be less than twice the power drawn from the auxiliary windings. (With synchronous switching, using the LTC1142, auxiliary outputs may be loaded without regard to the primary output load, providing that the loop remains in continuous mode operation.) Burst Mode operation can be suppressed at low output currents with a simple external network which cancels the 25mV minimum current comparator threshold. This technique is also useful for eliminating audible noise from
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certain types of inductors in high current (IOUT >5A) applications when they are lightly loaded. An external offset is put in series with the Sense- pin to subtract from the built-in 25mV offset. An example of this technique is shown in Figure 8. Two 100 resistors are inserted in series with the sense leads from the sense resistor.
SENSE + [PIN 16 (8)] 1000pF SENSE - [PIN 1(19)] R3 R2 100 R1 100 RSENSE VOUT
+
COUT
1143 F08
Figure 8. Suppression of Burst Mode Operation
With the addition of R3 a current is generated though R1 causing an offset of: VOFFSET = VOUT x
0V
)
R1 R1 + R3
)
0V
LTC1143 * F06
If VOFFSET > 25mV, the built-in offset will be cancelled and Burst Mode operation is prevented from occurring. Since VOFFSET is constant, the maximum load current is also decreased by the same offset. Thus, to get back to the same IMAX, the value of the sense resistor must be lower:
RSENSE 75mV IMAX
To prevent noise spikes from erroneously tripping the current comparator, a 1000pF capacitor is needed across pins 1 (16) and 9 (8). Board Layout Checklist When laying out the printed circuit board, the following checklist should be used to ensure proper operation of the LTC1143. These items are also illustrated graphically in the layout diagram of Figure 9. In general each block
13
LTC1143
APPLICATIONS INFORMATION
should be self-contained with little cross coupling for best performance. Check the following in your layout: 1) Are the signal and power grounds segregated? The LTC1143 ground pin 3 (11) must return separately to: a) the power, and b) the signal grounds. The power ground returns to the anode of the Schottky diode and (-) plate of CIN, which should have as short lead lengths as possible.The signal ground (b) connects to the (-) plate of COUT. 2) Does the LTC1143 Sense- pin 16 (8) connect to a point close to RSENSE and the (+) plate of COUT? 3) Are the Sense- and Sense+ leads routed together with minimum PC trace spacing? The 1000pF capacitor
P-CH
+
VIN5
+
CIN5
-
BOLD LINES INDICATE HIGH CURRENT PATHS SHUTDOWN (5V OUTPUT)
1k
GND5 SHUTDOWN 5 P-DRIVES5 SENSE -3
CT3
0.0033F
SENSE +5
ITH3
CT3 VIN3
1000pF*
SHUTDOWN 3 SENSE +3
LTC1143
SENSE - 5
0.22F*
P-DRIVES3 VIN5
GND3
SHUTDOWN (3.3V OUTPUT)
VIN5 1k CT5 0.0033F
RSENSE3
L2
P-CH
+ +
VOUT3 COUT3 D2
CT5
ITH5
-
Figure 9. LTC1143 Layout Diagram (see Board Layout Checklist)
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between pins 1 (9) and 16 (8) should be as close as possible to the LTC1143. 4) Does the (+) plate of CIN connect to the source of the P-channel MOSFET as closely as possible? This capacitor provides the AC current to the P-Channel MOSFET. 5) Is the VIN decoupling capacitor (1F, 0.1F) connected closely between pin 13 (5) and ground pin 3 (11)? This capacitor carries the MOSFET driver peak currents. 6) Are the Shutdown pins 2 and 10 actively pulled to ground during normal operation? Both shutdown pins are high impedance and must not be allowed to float. Both pins can be driven by the same external signal if needed.
L1 RSENSE5
+ +
COUT5 VOUT5
D1
-
VIN3
1000pF* 0.22F*
+ +
CIN3 VIN3
-
*MUST BE LOCATED CLOSE TO LTC1143
1143 F09
LTC1143
TYPICAL APPLICATIONS N
VIN 5.2V TO 14V CIN3 22F 25V x2 L1 50H
+
P-CH Si9430DY 4 1 0.01F 16 13 VIN3
VOUT3 3.3V/1A
RSENSE3 0.10
+
COUT3 220F 10V
D1 MBRD330
RSENSE3: IRC LR2512-01-OR100G RSENSE5: IRC LR2512-01-ORO5OG
Figure 10. All Surface Mount Dual 5V/2A, 3.3V/1A Converter
CIN3 22F 25V x2
+
P-CH Si9430DY 4 1 0.01F 16 13 VIN3
VOUT3 3.3V/2A
RSENSE3 0.05
L1 25H
+C
OUT3
220F 10V x2
D1 MBRD330
RSENSE3: KRL SL-1/2-C1-0R050J RSENSE5: KRL SL-1/2-C1-0R050J
Figure 11. All Surface Mount Dual 5V/2A, 3.3V/2A Converter
Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
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0.22F 0V = NORMAL >1.5V = SHUTDOWN 2 SHUTDOWN 3 10 SHUTDOWN 5 0.22F
+
5 VIN5 P-DRIVE 5 SENSE + 5 SENSE - 5 12 9 0.01F 8 P-CH Si9430DY
+
CIN5 22F 25V x2 L2 25H
P-DRIVE 3 SENSE + 3 SENSE - 3
RSENSE5 0.05
VOUT5 5V/2A
LTC1143
GND3 3
CT3 14
ITH3 15 RC3 1k CT3 270pF
ITH5 7 RC5 1k
CT5 6
GND5 11
D2 MBRD330
+
COUT5 220F 10V x2
CC3 3300pF
CC5 3300pF
CT5 220pF
LTC1143.F10
CIN3, CIN5: AVX (TA) TPSD226K025R0200 COUT3, COUT5: AVX (TA) TPSE227K010R0080
L2: COILTRONICS CTX50-4 L2: COILTRONICS CTX25-4
VIN 5.2V TO 14V
+
0.22F 2 SHUTDOWN 3 0V = NORMAL >1.5V = SHUTDOWN 0.22F 10 SHUTDOWN 5
+
5 VIN5 P-DRIVE 5 SENSE + 5 LTC1143 SENSE - 5 12 9 0.01F 8 P-CH Si9430DY
+
CIN5 22F 25V x2 L2 25H RSENSE5 0.05
P-DRIVE 3 SENSE + 3 SENSE - 3
VOUT5 5V/2A
GND3 3
CT3 14
ITH3 15 RC3 1k CT3 330pF CC3 3300pF
ITH5 7 RC5 1k
CT5 6
GND5 11
D2 MBRD330
+
COUT5 220F 10V x2
CC5 3300pF
CT5 220pF
LTC1143.F11
CIN3, CIN5: AVX (TA) TPSD226K025R0200 COUT3, COUT5: AVX (TA) TPSE227K010R0080
L1: COILTRONICS CTX25-4 L2: COILTRONICS CTX25-4
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LTC1143
PACKAGE DESCRIPTION
0.010 - 0.020 x 45 (0.254 - 0.508) 0.008 - 0.010 (0.203 - 0.254)
0 - 8 TYP
0.016 - 0.050 0.406 - 1.270
16
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7487
(408) 432-1900 q FAX: (408) 434-0507 q TELEX: 499-3977
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Dimensions in inches (millimeters) unless otherwise noted.
S16 Package 16-Lead Plastic SOIC
0.386 - 0.394* (9.804 - 10.008) 16 15 14 13 12 11 10 9
0.228 - 0.244 (5.791 - 6.197)
0.150 - 0.157* (3.810 - 3.988)
1 0.053 - 0.069 (1.346 - 1.752)
2
3
4
5
6
7
8
0.004 - 0.010 (0.101 - 0.254)
0.014 - 0.019 (0.355 - 0.483)
0.050 (1.270) TYP
SO16 0392
*THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.006 INCH (0.15mm).
LT/GP 0394 10K * PRINTED IN USA
(c) LINEAR TECHNOLOGY CORPORATION 1994

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